Red Echo

April 24, 2009

I haven’t done any work on Radian since late February. I’d like to get back into it, but it’s going to take a while to remember what I was doing and why. I was in the middle of a module which builds three-address intermediate code from a flowgraph, inverting the functional description into a list of imperative instructions…

4 Comments

  1. TAC? I thought you were going with SSA as the intermediate representation. Why the change of heart?

    Comment by Aaron Ballman — April 25, 2009 @ 2:07 am

  2. No change of heart: it starts out in SSA form.

    Comment by mars — April 25, 2009 @ 9:14 am

  3. There really is no one canonical intermediate representation, anyway; each interface between stages defines an IR. The parser emits an AST and the semantic analyzer accepts it; the analyzer emits a flowgraph for the atomizer, which emits an instruction series for the concretizer, and so on until the compiler emits machine code. It’s not so much that the intermediate representation *is* SSA, as that the language semantics are defined in terms of data flow, and thus any straightforward rendering of the flowgraph into imperative instructions will naturally obey the SSA constraint. It’s only after we start performing register allocation that the IR we produce loses this attribute.

    Comment by mars — April 25, 2009 @ 10:13 am

  4. Ahhh, ok, that makes more sense to me — thanks for the explanation!

    Comment by Aaron Ballman — April 25, 2009 @ 12:13 pm